The Halo synthesizer control panel

The hardware it drives

• A 56-bit 74HC165 shift-register chain reading the panel
• 16 rotary encoders, scanned at 1 kHz — tracks 250 detents/s at 4× quadrature decode
• 16 potentiometers via two analog muxes (IIR filtering + deadband)
• 20 buttons and 16 LEDs (74HC595, with blink states)
• Two HD44780 40×2 character LCDs
• A MIDI SysEx protocol link over UART at 921600 baud to the synthesizer host

Every one of those — every pin, chain bit, encoder phase, mux channel, LCD role — is a row in one board.hpp. Cross-references between them are consteval joins; conflicts are compile errors that name the offender. The typed handles the firmware uses are generated from the same tables by reflection.

What Firn bought

The whole panel in one data file

The topology is authored once, as data. Add a control, and a typed handle appears; wire two pots to the same mux channel, and the firmware does not compile.

A wire-compatible replacement

The firmware speaks a byte-identical wire protocol to its predecessor — the synthesizer host cannot tell them apart. Runtime-tunable parameters (firn::Editable: type, range, precision, response curve) are pushed by the host over SysEx, with pub/sub display and change callbacks — the same concept shared between the firmware and the host UI.

It found real bugs in the original

Rebuilding on Firn surfaced and fixed two latent defects in the firmware it replaces: a TX frame-drop race in the protocol path, and a linker-script hole that silently discarded all global constructors.

Golden-tested against a simulator

The firmware also builds as a host simulation, golden-tested end-to-end — including an HD44780 protocol decoder that drives the real LCD driver code, so what the simulator renders is what the panel's LCDs show. Then it was verified on the physical panel over its SysEx/UART link.

A real RTOS, with exceptions

The firmware runs as threads on µOS++ IIIe: a 1 kHz input-scan thread, a semaphore-driven protocol thread woken from the USART ISR, mutex-guarded shared buses. All 17 on-target RTOS feature tests pass on the real silicon — threads, mutexes under contention, semaphores including post-from-ISR, message queues, event flags, timers, memory pools, condition variables, heap, and C++ exceptions (class-hierarchy catches, RAII unwinding, throw inside a thread) — on a Cortex-M0+.

What this page is for

Every claim on this site is either regression-tested in the framework repository or demonstrated by this firmware on real hardware. The panel is the demonstration: topology-as-data, compiler validation, reflection-generated handles, generic drivers bound by an Io policy, compile-time pub/sub, and the C ↔ C++ bridge — all of it, at once, in one shipping firmware.

Want the mechanics? How it works. Want to try it? Get started.